Marvell’s Structera CXL Chips Aim to Stretch Memory Capacity as AI Demand Drives Shortages

Marvell has introduced two new CXL memory controllers designed to help data centers use available memory more efficiently. The Structera X and Structera A chips use built in hardware compression to reduce the amount of DRAM needed for data, an approach that could become more valuable as AI workloads continue to strain global memory supply.

The new controllers are aimed at large server systems rather than consumer PCs. They use Compute Express Link, or CXL, a technology that allows processors, accelerators, and memory expansion hardware to share resources more efficiently inside data centers.

Marvell’s main claim is that its Structera platform can compress data in real time as it is written to memory and decompress it when it is read back. This happens through a dedicated Compression Decompression Block, allowing the work to take place without using host CPU resources.

That could help companies increase usable memory capacity without installing as much additional DRAM, while also reducing pressure on bandwidth in AI focused systems.

Structera Uses Hardware Compression Instead of CPU Resources

Most data compression is handled in software, which can consume processor time and add delays. Marvell’s approach places a dedicated compression engine directly inside the controller.

The hardware uses a custom implementation of the LZ4 compression algorithm, which is designed to provide low latency while still offering useful compression ratios. The process is lossless, meaning the original data can be restored without changes.

Marvell says this allows data to be compressed at full bandwidth as it enters DRAM. When an application needs that data again, the controller decompresses it in real time.

The actual gains will depend heavily on the type of data being stored. Some workloads compress well, while others offer limited room for improvement. All zero memory pages can reportedly reach much higher ratios, though that is not representative of typical real world use.

Structera X Focuses on Memory Expansion

Structera X is built as a CXL memory expansion controller. It supports both DDR5 and DDR4 memory, giving data center operators a way to use newer modules while maintaining compatibility with older infrastructure.

The chip supports CXL 2.0 and PCIe 5.0 connections, with up to 200GB per second of memory bandwidth. It includes four memory channels, support for several DIMMs per channel, 56MB of last level cache, encryption, secure boot, and hardware security features.

Marvell says Structera X can support more than 6TB of DDR5 memory capacity or more than 4TB of DDR4 memory capacity. That makes it suitable for large databases, cloud platforms, AI systems, and enterprise workloads that need extensive memory pools.

Structera A Adds Near Memory Processing

Structera A is designed for near memory acceleration. Along with the compression engine, it includes 16 Arm Neoverse V2 processor cores running at up to 3.2GHz.

The extra processing resources allow the controller to perform work closer to memory, reducing the amount of data that has to travel back to the main system processor. This can be useful for AI inference, analytics, database processing, and other workloads where moving data becomes a major performance bottleneck.

Structera A also supports CXL 2.0 and PCIe 5.0, delivers up to 200GB per second of bandwidth, and includes four DDR5 6400 memory channels.

Memory Efficiency Is Becoming More Important for AI Infrastructure

AI data centers require huge amounts of memory for model training, inference, storage, and data processing. At the same time, high demand for DRAM, HBM, and enterprise storage has increased costs across the industry.

Marvell’s Structera chips will not solve the broader memory shortage, but they could help companies get more value from the capacity they already have. Hardware based compression may allow some workloads to fit into smaller memory pools while freeing CPU resources for other tasks.

As AI infrastructure becomes larger and more expensive, improving memory efficiency could be just as important as increasing raw compute performance.