Intel Says Closing Technology Gap With TSMC Matters Less Than Manufacturing Scale and Execution

Intel believes it has largely caught up with TSMC in semiconductor manufacturing technology, although matching the Taiwanese company's production capacity will take considerably longer.

During a recent technology discussion, Intel chief technology officer Pushkar Ranade explained that small differences in chip performance, power efficiency, or transistor density are less important than delivering manufacturing processes on schedule.

Meanwhile, Intel vice president Chris Auth defended the company's decision to adopt High NA EUV lithography, arguing that its backside power delivery technology provides advantages over conventional chip manufacturing approaches.

Intel Says High NA EUV Works Better With Backside Power Delivery

Intel is preparing its 14A manufacturing process with High NA EUV lithography, a technology designed to print increasingly smaller circuit features onto silicon wafers.

High NA EUV improves lithography resolution, potentially allowing manufacturers to produce certain patterns in a single exposure rather than using multiple patterning steps.

Backside power delivery relocates power connections behind the silicon wafer, freeing valuable space on the front for transistors and signal connections.

This reduces some wiring density requirements and provides greater flexibility when printing circuits.

Auth argued that TSMC faces tighter pitch requirements because of differences in its power delivery approach, potentially requiring additional patterning steps.

Intel currently offers High NA EUV as an option for its 14A process, with implementation decisions depending on individual customers.

Intel CTO Emphasizes Manufacturing Yield and Production Capacity

Ranade acknowledged that TSMC manufactures substantially more wafers than Intel.

He described closing this production capacity gap as a gradual process requiring sustained investment and execution.

However, he argued that Intel is already competitive technologically, even if individual manufacturing metrics differ by several percentage points.

According to Ranade, maintaining high production yields and meeting development schedules are more important than achieving marginal improvements in performance or transistor density.

These factors determine whether a manufacturer can efficiently produce advanced chips at commercial volumes.

Intel Highlights Challenges With Future Stacked Transistors

Intel researchers also discussed the difficulties associated with stacking different transistor types vertically.

Jack Kavalieros, an Intel research executive, explained that connecting vertically stacked transistors presents significant manufacturing challenges.

Creating and filling increasingly narrow vertical connections can introduce defects, including unwanted gaps and voids.

These problems must be addressed before advanced stacked transistor designs can become commercially practical.

Intel's comments highlight its confidence in upcoming manufacturing technologies while acknowledging that competing with TSMC requires reliable production and greater manufacturing scale.