TSMC is reportedly accelerating work on CoPoS, a new panel level advanced packaging technology designed to support larger AI and high performance computing chips at lower cost. The approach could eventually reduce reliance on today’s CoWoS packaging by using larger rectangular panels and glass core substrates to improve material use, chip capacity, and manufacturing efficiency.
The shift is being driven by rapidly growing demand for AI accelerators, data center processors, and huge multi chip packages. Existing CoWoS technology remains important, but circular wafers create limits when package sizes continue to grow. CoPoS is intended to address those limits by moving advanced packaging onto much larger square or rectangular panels.
TSMC is expected to begin trial production for CoPoS in 2027, with broader mass production targeted for 2028. Glass core substrate versions are expected later, with reports pointing toward the 2030 period.
CoPoS could replace circular wafers with larger panels
CoWoS stands for Chip on Wafer on Substrate. It is widely used for advanced chips that combine GPUs, AI processors, high bandwidth memory, and other components into one large package.
CoPoS, or Chip on Panel on Substrate, changes the manufacturing format. Instead of working only with a circular 300mm wafer, it uses much larger panels that can be square or rectangular.
This can improve usable surface area and reduce the amount of material wasted around the edges.
| Packaging technology | Main format | Potential advantage |
|---|---|---|
| CoWoS | Circular wafer | Proven technology for advanced AI packages |
| CoPoS | Large square or rectangular panel | Higher package capacity and better material use |
| Glass core substrate | Glass layer inside substrate | Better scaling, lower cost potential, and improved stability |
Reports suggest CoPoS panels could reach sizes as large as 750mm by 620mm. TSMC has also discussed smaller panel formats, including 310mm by 310mm and 515mm by 510mm.
These larger surfaces could allow more compute dies, memory modules, and interposers to be produced in a single manufacturing run.
Glass core substrates could improve yields and lower costs
Glass core substrates are expected to play a major role in TSMC’s long term packaging roadmap. Traditional substrate designs often rely heavily on organic materials and silicon components. Glass offers better dimensional stability and may support larger package designs more efficiently.
The reported benefit is not only technical. Glass could also help lower production costs as package sizes increase.
Panel level packaging may deliver around 20% to 30% lower cost per unit area compared with conventional wafer based approaches. It could also improve material utilization beyond 90%, compared with lower efficiency from circular wafers.
That matters because AI chips are becoming physically larger and more expensive. The biggest accelerators now combine multiple compute dies with stacks of high bandwidth memory, making packaging one of the most important parts of chip production.
AI chips are pushing advanced packaging beyond current limits
The demand for AI hardware has changed how chip companies think about packaging. In the past, packaging was often treated as a final manufacturing stage. Now it is a major performance, cost, and capacity factor.
Modern AI accelerators need large amounts of HBM memory placed close to the processor. They also need fast interconnects between compute dies, memory stacks, and networking components.
As these packages grow, circular wafers become less efficient. A large rectangular package placed on a round wafer can leave unusable areas around the edges. Panel level production reduces that geometric waste.
| AI packaging challenge | How CoPoS may help |
|---|---|
| Larger accelerator designs | Supports bigger multi die packages |
| More HBM memory stacks | Provides more usable panel space |
| High production costs | Reduces waste per unit area |
| Limited packaging capacity | Increases potential package output |
| Larger future chip designs | Offers a path beyond current CoWoS limits |
This is why CoPoS is being viewed as a next generation option for AI and data center hardware rather than a simple replacement for current packaging methods.
TSMC is also working on glass for CoWoS
CoPoS is not the only area where TSMC is exploring glass substrates. The company is also developing glass based approaches for its existing CoWoS packaging technology.
This could give TSMC a gradual path forward. CoWoS can continue serving current customers while glass substrate technology improves manufacturing efficiency and prepares the company for larger panel level designs.
Reports indicate that TSMC is working with substrate and display technology partners on a design that uses glass positioned between ABF layers. ABF substrates are already important for high end processors, GPUs, and data center chips.
The goal is to create a substrate that can handle larger designs without raising costs as sharply as existing solutions.
Intel is also investing heavily in glass substrate technology
TSMC is not alone in this area. Intel has been developing glass substrate technology for advanced chip packaging and has already shown early work around large scale panel level solutions.
The two companies are expected to become major competitors in the next phase of advanced packaging. Intel has its own technologies, including EMIB, while TSMC remains the leading supplier of CoWoS for many major AI chip companies.
Glass core substrates could become a major battleground because they may determine who can build the largest and most efficient AI packages during the next decade.
CoPoS may become important for future AMD and AI products
The technology is expected to matter far beyond one company or one chip category. AI accelerators are the clearest use case, but panel level packaging could also be important for future CPUs, GPUs, networking processors, and custom data center chips.
AMD has already been linked with TSMC’s broader panel level packaging plans for future Zen based products. As chiplet designs become more common, packaging will become even more important for combining several small dies into one powerful product.
CoPoS will not replace CoWoS overnight. CoWoS remains central to current AI chip production, and TSMC will continue expanding it. However, CoPoS and glass core substrates could become essential once package sizes and AI memory requirements move beyond what current wafer based manufacturing can handle.
TSMC’s reported 2027 trial timeline and 2028 mass production target show that the industry is preparing early for that transition.
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