TSMC Could Raise CoWoS Packaging Prices by 20% as AI Chip Demand Strains Production Capacity

TSMC is reportedly considering a price increase of up to 20% for its CoWoS advanced packaging technology as growing demand for AI processors puts additional pressure on manufacturing capacity.

The potential increase comes as chipmakers develop increasingly complex AI accelerators that combine multiple computing dies with high bandwidth memory (HBM).

According to supply chain reports, these designs require more manufacturing resources and longer testing periods, creating bottlenecks that could affect production schedules.

However, TSMC has not officially confirmed the proposed price increase, and negotiations with customers remain unverified.

Complex AI Chips Are Increasing CoWoS Manufacturing Costs

CoWoS, short for Chip on Wafer on Substrate, allows manufacturers to combine multiple semiconductor dies and memory stacks within a single package.

The technology is widely used in advanced AI accelerators that require high memory bandwidth and efficient communication between components.

As manufacturers increase the number of computing dies and HBM stacks, packaging becomes more complicated.

Larger packages can also reduce equipment throughput, meaning manufacturing facilities may produce fewer units within the same period.

Testing these complex processors requires additional time, placing pressure on both packaging and validation capacity.

These challenges are reportedly contributing to discussions about higher pricing.

TSMC Plans Major CoWoS Capacity Expansion Through 2028

TSMC is reportedly expanding its advanced packaging capacity to address rising demand from AI hardware companies.

Capacity milestone	Reported target
2026	130,000 wafers monthly
2027	200,000 wafers monthly
2028	Expected US facility production

The reported figures have not been independently confirmed.

Equipment delivery times have reportedly increased from three to six months to approximately six to eight months.

Industry estimates also suggest that new advanced packaging facilities can require around three years to reach full production capacity.

Intel EMIB Remains an Alternative to TSMC CoWoS

Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology offers a different approach to connecting semiconductor dies.

While CoWoS uses a silicon interposer for dense communication between chips, EMIB relies on smaller silicon bridges embedded within the package substrate.

EMIB can reduce silicon usage, but suitability depends on the complexity and connectivity requirements of individual designs.

TSMC is also developing larger CoWoS packages and its CoPoS technology to support future AI processors.

For now, established manufacturing processes and existing customer relationships may help TSMC maintain strong demand even if packaging prices increase.

A confirmed 20% increase could raise production costs for AI accelerators, although the eventual impact on customers would depend on individual supply agreements.