IBM has detailed a next generation processor design that can execute both native z/Architecture and Arm AArch64 software on the same core, rather than combining separate CPU types or relying on emulation. The company says the dual ISA core is being developed for future IBM Z and LinuxONE systems.
The design is intended to bring the Arm software ecosystem directly into IBM’s mainframe platform while preserving the performance, scalability, availability and security features associated with IBM Z.
IBM dual ISA processor specifications
| Feature | Detail |
|---|---|
| ISA support | Native z/Architecture and Arm AArch64 |
| Core count | 11 IBM Z cores |
| Clock speed | Above 5.7 GHz |
| Process | 2nm |
| Private L2 cache | 36MB |
| Virtual L3 cache | 432MB |
| Combined L4 cache | Up to 3.5GB |
| Accelerators | DPU, AI, compression, cryptography and sort |
| Virtualization | KVM support for S390X/Z and Arm64 |
| Status | Preparing for tape out |
IBM says the processor will contain 11 cores operating above 5.7 GHz and will be manufactured on a 2nm process. Each core will support both IBM Z instructions and Arm AArch64 execution natively.
This is not a hybrid core design
The most important distinction is how IBM is implementing Arm support.
This is not a design similar to Intel processors with different Performance and Efficiency cores on the same package. IBM is also not describing a software emulation layer.
Instead, Arm ISA support is being integrated directly into the mainframe core itself.
That means a single core can execute software built for either z/Architecture or Arm AArch64.
IBM’s goal is to make it easier for enterprises to run Arm based applications alongside traditional mainframe workloads without moving those applications to a separate server platform.
Cache capacity is unusually large
IBM is also emphasizing the processor’s cache hierarchy.
Each core will have 36MB of private L2 cache, while the design combines those caches into larger virtual cache structures.
The virtual L3 cache reaches 432MB, while the L4 layer can provide as much as 3.5GB.
Those large, low latency caches are intended for enterprise applications such as transaction processing and databases, where memory access delays can have a major effect on performance.
Arm workloads gain access to IBM accelerators
The processor will include several dedicated acceleration blocks.
IBM lists an on chip DPU for I/O acceleration alongside hardware for AI, compression, cryptography and sorting.
Importantly, those capabilities will also be available to Arm software running on the system.
This could allow Arm applications to use the same enterprise acceleration hardware as traditional IBM Z workloads rather than being isolated from the platform’s specialized features.
Virtualization will support both architectures
IBM Z already relies heavily on virtualization.
Enterprises commonly run core workloads under z/OS while also operating Linux environments through technologies such as KVM and OpenShift.
The future processor is designed to extend that model by supporting KVM virtual machines using both traditional S390X/Z and Arm64 architectures.
That could let organizations place Arm Linux workloads closer to existing mainframe applications while keeping them inside the same system architecture.
IBM Z and LinuxONE remain important enterprise platforms
IBM says its Z and LinuxONE systems run 68% of the world’s production IT workloads, while 77 of the world’s 100 largest banks use the platforms.
That gives IBM a large installed base for introducing Arm compatibility without asking customers to abandon their existing mainframe infrastructure.
The strategy appears to be less about replacing z/Architecture and more about widening the range of software that can run beside it.
Tape out is approaching
IBM says the dual ISA processor is still several years away from deployment, but the company is preparing to send the design for tape out.
No exact launch date has been announced.
The project remains focused on IBM Z and LinuxONE, and IBM has not announced support for additional operating systems beyond the current plans.
If the design reaches production as described, it would give IBM a processor capable of executing two major instruction sets directly within the same core, potentially simplifying mixed enterprise environments that currently separate mainframe and Arm workloads across different systems.
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