AMD has confirmed that its EPYC Verano and EPYC Venice-X server processors will launch in 2027, expanding the company’s Zen 6 portfolio for agentic AI, high-performance computing and memory-intensive workloads.
The two product families are designed for different parts of the data centre market. Venice-X will focus on technical computing and HPC through very large 3D V-Cache capacity, while Verano will combine high clock speeds with LPDDR5X memory and faster CPU-to-GPU connectivity for AI systems.
Venice-X is expected to offer up to 96 cores and 192 threads in a single processor. Dual-socket platforms could therefore provide as many as 192 Zen 6 cores and 384 threads.
AMD is also targeting clock speeds above 5GHz, with a reported maximum of around 5.15GHz. The largest configuration will include up to 1,152MB of L3 cache, making Venice-X one of AMD’s most cache-heavy server processors.
| Processor family | Main focus | Maximum cores | Maximum threads | Key feature |
|---|---|---|---|---|
| EPYC Venice-X | HPC and technical computing | 96 | 192 | Up to 1,152MB of L3 cache |
| EPYC Verano | Agentic AI and GPU servers | 72 | 144 | LPDDR5X through SOCAMM2 |
| EPYC Venice Dense | Dense cloud computing | 256 | 512 | Zen 6c core architecture |
| Standard EPYC Venice | General-purpose servers | 96 | 192 | Zen 6 and PCIe 6.0 |
Venice-X uses 3D V-Cache to improve technical computing performance
Venice-X will extend AMD’s use of vertically stacked cache in the data centre.
The processors reportedly place 3D V-Cache beneath the Zen 6 compute cores. This design increases the amount of addressable cache available to each core while preserving the processor’s overall platform structure.
Large cache capacity can improve workloads that repeatedly access the same datasets. Scientific simulation, computational fluid dynamics, electronic design automation and other technical applications can benefit when more data remains close to the processor rather than being fetched from system memory.
The top Venice-X model is expected to provide 1,152MB of L3 cache.
That figure is significantly higher than the cache available on standard Venice processors. AMD also claims around 50 percent more addressable cache per core compared with some earlier configurations.
The company is pairing that cache with clock speeds above 5GHz, which could help workloads that rely on both high single-thread performance and large shared datasets.
Microsoft has already indicated that Venice-X processors will be used in its Azure HXv2 cloud instances. These systems are expected to target demanding HPC and technical computing customers.
Memory bandwidth will be another major part of Venice-X
Venice-X will support DDR5-8000 and high-speed MRDIMMs reaching up to 12,800 MT/s.
The SP7 platform is expected to provide 16 memory channels, giving the processors access to substantial memory bandwidth.
This matters because large cache alone cannot eliminate the need to move data from main memory. Many HPC workloads process datasets that are far larger than any cache can hold.
The combination of 3D V-Cache and fast 16-channel memory should help reduce bottlenecks across a broader range of applications.
The processors will also support PCIe 6.0, allowing faster connections to accelerators, storage and networking devices.
Maximum power consumption may reach around 600W on some Venice configurations, reflecting the demands of high core counts, fast memory and large cache capacity.
Verano is designed for agentic AI infrastructure
EPYC Verano takes a different approach.
The processors will use the same Zen 6 core architecture but will be part of the EPYC 9006 LP family. They are expected to offer up to 72 cores and 144 threads.
Verano is designed for systems that coordinate AI agents and feed data to large accelerator clusters.
The processors will support CPU-to-GPU connectivity of up to 112Gbps through xGMI. AMD expects this link to connect Verano CPUs with future Instinct MI500 accelerators in next-generation AI racks.
Agentic AI systems may involve many models, tools and software processes operating at the same time. The CPU must manage scheduling, memory, networking and communication with accelerators while maintaining low latency.
Higher CPU frequency can be useful in these environments because some orchestration tasks are difficult to distribute across very large numbers of cores.
Verano therefore appears to prioritise a balance between core count, frequency, memory efficiency and accelerator connectivity.
SOCAMM2 brings LPDDR5X to AMD server platforms
Verano will be AMD’s first server processor to support SOCAMM2 memory.
SOCAMM2 is a compact, replaceable memory form factor designed around LPDDR5X. It aims to combine high bandwidth and large capacity with lower power use than traditional server memory in some configurations.
The modules can be installed in dense AI systems where space and energy efficiency are important.
Micron has already begun shipping 256GB SOCAMM2 modules to infrastructure partners. Similar memory is expected to appear in NVIDIA’s Vera CPU platforms and other AI-focused systems.
Verano will use the SP8 platform and may support up to eight memory channels.
The use of LPDDR5X should reduce power consumption compared with conventional memory designs, which is valuable in racks where GPUs already consume substantial amounts of electricity.
The trade-off is that increased demand from AI servers could place further pressure on the LPDDR supply chain.
AI servers may increase competition for LPDDR memory
LPDDR memory is widely used in smartphones, laptops and other power-efficient devices.
Its growing use in AI infrastructure could create additional competition between consumer electronics and data-centre customers.
AI vendors often purchase memory in large volumes and may be willing to pay higher prices because the value of a complete rack is far greater than the cost of an individual module.
This could make supply tighter for other parts of the technology market.
NVIDIA’s Vera Rubin and Vera CPX platforms are also expected to use SOCAMM2 LPDDR5X. Other accelerator and inference platforms are reportedly moving in the same direction.
If these systems enter mass production at the same time, memory suppliers may need to expand capacity quickly to prevent shortages and price increases.
Zen 6 gives AMD a broader EPYC product range
AMD’s sixth-generation EPYC family will include several designs rather than a single general-purpose processor.
Standard Venice will target broad server workloads. Venice Dense will use Zen 6c cores and scale to as many as 256 cores and 512 threads. Venice-X will focus on cache-heavy technical computing, while Verano will address AI orchestration and high-frequency server tasks.
This product segmentation allows AMD to compete across cloud computing, HPC, AI infrastructure and enterprise servers without forcing every customer into the same design.
The approach also reflects how specialised the server market has become.
Some customers prioritise maximum core density. Others need very large cache, high clock speeds, low power memory or direct links to accelerators.
EPYC Verano and Venice-X are expected to launch in 2027. Final model names, prices, power limits and complete platform configurations have not yet been announced, but AMD has made clear that both products will play important roles in its Zen 6 data-centre strategy.
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