AMD has officially introduced its sixth-generation EPYC Venice processor family, bringing Zen 6 cores, TSMC’s 2nm process technology and configurations reaching 256 cores and 512 threads.
The new EPYC 9006 lineup covers several server markets, including dense agentic AI systems, general-purpose enterprise servers, high-frequency workloads and technical computing. AMD is also positioning Venice as a direct competitor to NVIDIA’s Vera CPU, claiming up to 20% higher single-core performance and as much as 2.2 times greater throughput in selected workloads.
The largest Venice processor contains up to 203 billion transistors. AMD uses TSMC’s 2nm process for the compute chiplets and a 6nm process for the input output dies.
AMD says the new generation provides more than an 80% improvement in performance and efficiency, alongside over 30% higher thread density. These are company benchmark claims and will require independent testing across real production workloads.
| EPYC Venice feature | Maximum specification |
|---|---|
| CPU architecture | Zen 6 |
| Process technology | TSMC 2nm compute, 6nm input output |
| Core count | 256 |
| Thread count | 512 |
| Transistor count | 203 billion |
| Maximum clock speed | Up to 5GHz on selected models |
| Memory bandwidth | Up to 1.6TB/s |
| PCIe support | PCIe 6.0 |
| Maximum L3 cache | Up to 1,152MB on Venice-X |
| Maximum power | Up to 600W on selected SP7 models |
EPYC 9006 SP7 targets dense AI and cloud systems
The flagship SP7 family is designed for high-density servers and large agentic AI deployments.
The top EPYC 9996 includes 256 cores and 512 threads, with a base clock of 2.55GHz and boost speeds reaching 4.1GHz. It also carries 1,024MB of L3 cache and a 600W default power rating.
AMD lists the processor at $14,904 in quantities of 1,000 units.
Other SP7 models reduce core count while increasing clock speed. The EPYC 9686F, for example, uses 96 cores and can boost to 5GHz. It is intended for workloads that benefit from stronger per-core performance rather than maximum thread density.
The SP7 platform supports PCIe 6.0 and memory bandwidth reaching 1.6TB/s. AMD says this combination can help keep accelerators, networking devices and storage systems supplied with data.
The first SP7 Venice processors are scheduled to ship during the fourth quarter of 2026.
| Selected SP7 processor | Cores and threads | Maximum boost | L3 cache | Power | Price |
|---|---|---|---|---|---|
| EPYC 9996 | 256 and 512 | 4.1GHz | 1,024MB | 600W | $14,904 |
| EPYC 9966 | 192 and 384 | 4.0GHz | 768MB | 600W | $14,079 |
| EPYC 9756 | 128 and 256 | 4.0GHz | 512MB | 500W | $12,498 |
| EPYC 9686F | 96 and 192 | 5.0GHz | 384MB | 500W | $11,434 |
| EPYC 9586F | 64 and 128 | 5.0GHz | 384MB | 500W | $9,701 |
SP8 brings Venice to smaller and more efficient servers
AMD is also introducing EPYC 9006 processors for the SP8 platform.
These models cover a wider range from eight to 128 cores and are intended for enterprise servers, edge systems, smaller clusters and power-constrained environments.
SP8 supports eight DDR5 memory channels, two DIMMs per channel and 128 PCIe 6.0 lanes. It can be deployed in single-socket or dual-socket configurations.
The range includes high-frequency processors reaching 5GHz as well as lower-power models designed for more modest workloads.
The entry-level EPYC 9016 includes eight cores and 16 threads, a 4.8GHz maximum boost clock and a 130W power rating. Its listed price is $700.
At the upper end, the EPYC 9746 provides 128 cores and 256 threads with a maximum boost clock of 4GHz.
AMD plans to ship SP8 Venice processors during the first half of 2027.
AMD claims major gains over NVIDIA Vera
AMD is presenting Venice as a stronger CPU option for AI servers than NVIDIA’s Arm-based Vera processor.
The company claims up to 1.2 times higher single-core performance and 2.2 times greater throughput compared with Vera.
It also reports up to 2.8 times more AI agents per watt in agentic CPU server workloads and up to 3.3 times more performance per watt in general-purpose servers.
These comparisons are based on AMD’s own testing and may depend heavily on server configuration, software, memory, workload size and power limits.
Single-core performance matters in AI infrastructure because not every task can be distributed efficiently across hundreds of cores. Scheduling, orchestration, tool use and request routing can still rely on strong per-thread performance.
Throughput becomes more important when large numbers of AI agents or software processes run at the same time.
AMD believes Venice can address both requirements by combining very high core counts with selected high-frequency models.
Agentic AI is changing the role of server CPUs
GPUs perform most of the large matrix calculations in modern AI systems, but CPUs remain responsible for coordinating the rest of the workload.
An agentic AI system may involve several models, external tools, databases and reasoning stages. The processor must schedule those tasks, prepare data and manage communication between accelerators.
This creates demand for more CPU threads, faster memory and stronger input output connectivity.
AMD says Venice can deliver up to 1.8 times more tokens per second, 1.7 times more agents per watt and 1.4 times more performance per watt than its previous EPYC Turin generation.
The 256-core EPYC 9996 also showed strong company benchmark results in tasks such as context retrieval, tool execution, response streaming and request routing.
The performance claims suggest AMD is optimising Venice for workloads beyond traditional web hosting and virtual machines.
Zen 6 uses TSMC’s 2nm nanosheet process
Venice is the first high-performance computing CPU family described as entering volume production on TSMC’s 2nm node.
The process moves from FinFET transistors to a nanosheet gate-all-around design.
TSMC claims the technology can provide 10% to 15% higher performance at the same power, 25% to 30% lower power at the same performance and up to 15% greater transistor density.
AMD uses the advanced node for the compute dies, while the input output dies remain on a mature 6nm process.
This mixed-node chiplet approach allows AMD to reserve the more expensive manufacturing technology for the parts that benefit most from it.
The design uses up to eight compute dies and two input output dies in the largest configuration.
Venice-X and Verano will expand the family in 2027
The broader EPYC 9006 range will eventually include Venice-X and Verano models.
Venice-X will target technical computing and memory-sensitive workloads with 3D V-Cache and as much as 1,152MB of L3 cache.
Selected Venice-X processors are expected to reach approximately 5.15GHz. They will support DDR5-8000 and high-speed MRDIMMs reaching 12,800 MT/s across 16 memory channels.
Verano, now branded EPYC 9006 LP, will serve as an AI host processor for dense rack-scale systems.
It will use LPDDR5X memory through SOCAMM2 modules and provide high-speed links to future Instinct accelerators.
Together, these products give AMD separate options for maximum core density, high frequency, large cache and power-efficient AI hosting.
The standard SP7 Venice family begins shipping in late 2026, while SP8, Venice-X and Verano products are expected to expand the Zen 6 server portfolio throughout 2027.
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