Samsung and SK hynix are reportedly working on different ways to build future DRAM chips as AI demand puts more pressure on the memory market.
AI data centers need large amounts of memory, including HBM and advanced DRAM. That demand has tightened supply across the industry and pushed memory makers to find new ways to increase density and performance.
The challenge is that DRAM becomes harder to shrink as chip designs get smaller. Unlike normal processors, DRAM has to store data inside a capacitor. That capacitor works with a transistor, and as memory cells get smaller, keeping enough charge inside each cell becomes more difficult.
This is why memory companies are looking beyond traditional 2D DRAM designs. The industry is moving toward 3D DRAM, where different structures can be arranged in new ways to keep improving density.

Samsung is reportedly looking at a method that uses GAAFET technology. In processors, GAAFET wraps the transistor gate around the channel, giving better control over current flow. Samsung wants to apply a similar idea to DRAM, but it also has to fit the capacitor into the memory cell.
One possible Samsung approach is to borrow a technique from NAND production. The company may place the control circuitry under the memory array, similar to how some NAND chips are built. That could help free up space and improve scaling.
SK hynix is said to be testing a different method known as 4F². This approach uses vertically stacked transistors with gate material wrapped around them. It also places some components below the transistor pillar to improve layout efficiency.
Here is the simple comparison:
| Company | Reported approach | Main idea |
|---|---|---|
| Samsung | GAAFET based DRAM with NAND like layout ideas | Use transistor gate wrapping and place circuitry under the memory array |
| SK hynix | 4F² vertical stacking | Stack transistors vertically with gate material wrapped around them |
| Shared goal | Next generation DRAM | Improve density, scaling, and performance for AI era memory |
Both companies appear to be trying to shape the future standard for DRAM manufacturing. Whoever proves its method first could gain an important advantage as AI workloads drive higher demand for memory.
The timing matters because memory is becoming one of the most important parts of AI infrastructure. GPUs and accelerators get much of the attention, but they need fast and dense memory to keep working efficiently. Better DRAM designs could help future AI systems handle larger models and heavier workloads.
For now, these approaches are still part of the race toward next generation memory. Samsung is leaning on ideas from advanced transistor design and NAND manufacturing, while SK hynix is pushing vertical stacking. The winner may help define how DRAM evolves beyond today’s scaling limits.



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