Qualcomm has successfully validated its first generation High Bandwidth Compute (HBC) silicon, reporting an 18 times improvement in effective memory bandwidth compared with conventional LPDDR5X implementations.
The company conducted testing at its San Diego laboratories, where the technology also demonstrated more than five times the projected bandwidth efficiency per watt of HBM4 memory.
The results represent an important development in Qualcomm's effort to improve AI inference performance while reducing the energy required to move data between processors and memory.
Qualcomm plans to introduce the technology commercially through its Dragonfly AI accelerator family, beginning with the Dragonfly AI250 platform in 2027.
Qualcomm HBC Uses Vertically Stacked Memory to Improve Efficiency
The HBC architecture places low power LPDDR memory directly above an AI accelerator's processing die.
Instead of moving information across relatively longer connections between separate components, the design uses direct wafer bonding to shorten the distance between memory and computing logic.
This arrangement allows data to move over micrometer distances, potentially reducing latency and power consumption.
The approach specifically targets AI inference workloads, where processors frequently need to access large amounts of model data.
During laboratory testing, Qualcomm used a prototype containing two stacked DRAM layers.
Future commercial implementations are expected to use four layers, providing greater memory capacity.
The company has also developed redundancy and remapping techniques intended to reduce manufacturing problems associated with stacking multiple silicon layers.
Early Testing Shows Major Memory Bandwidth Improvements
Qualcomm's laboratory validation used automated equipment and randomized AI workloads to assess the technology.
The company reported improvements in both effective bandwidth and energy efficiency.
| Measurement | Reported result |
|---|---|
| Effective memory bandwidth | 18 times LPDDR5X implementations |
| Bandwidth efficiency | Over 5 times projected HBM4 efficiency |
| Prototype memory layers | 2 |
| Planned commercial memory layers | 4 |
| First commercial platform | Dragonfly AI250 |
| Customer sampling | First half of 2027 |
These figures come from Qualcomm's internal testing and have not yet been established through independent production system benchmarks.
The reported energy efficiency improvement also fell slightly below Qualcomm's earlier target of six times the bandwidth efficiency of HBM4.
Dragonfly AI250 Will Arrive in 2027
Qualcomm plans to begin sampling its Dragonfly AI250 accelerator to enterprise customers and large cloud providers during the first half of 2027.
A complete liquid cooled Dragonfly AI250 rack is designed to offer 38.6TB of system memory and 7.4 petabytes per second of effective memory bandwidth.
The company is also preparing its custom Oryon based C1000 server processor for release in 2027.
A subsequent Dragonfly AI300 platform featuring next generation HBC technology is planned for 2028.
These products are intended to address increasing demand for AI inference infrastructure as organizations deploy larger language models and automated AI agents.
Although the early results are promising, commercial performance, manufacturing yields and overall system costs remain important factors.
Qualcomm's HBC technology could provide an alternative approach to AI memory design if its laboratory efficiency advantages translate successfully into large scale deployment.
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