Intel Wildcat Lake Cuts Platform Costs by Replacing Foveros With UCIe Based Multi Chip Packaging

Intel has detailed how its Wildcat Lake Core Series 3 processors reduce cost compared with Panther Lake, with one of the biggest changes being the move away from Foveros packaging to a simpler organic multi chip package connected through UCIe.

Wildcat Lake is designed for more affordable PCs and other mainstream systems while keeping modern features such as Thunderbolt 4, Wi Fi 7 and Bluetooth 6. Intel also positions the platform for areas beyond laptops, including robotics, smart buildings and meeting systems.

Wildcat Lake uses a simpler two die package

Area	Wildcat Lake approach
Packaging	Organic multi chip package
Die connection	UCIe
Compute process	Intel 18A
I/O process	TSMC N6
Base die	Removed
Package size	35 x 25 x 1.23 mm
Panther Lake comparison	50 x 25 x 1.5 mm for 4 Xe design
Memory bus	64 bit LPDDR5
Main goal	Lower platform and assembly cost

Intel said it considered a monolithic design but chose the multi chip package because it offered better overall value for this product class. The compute die uses Intel 18A, while the I/O tile uses TSMC N6.

Removing the Foveros base die cuts assembly cost and reduces some yield losses. The simpler package also allows Intel to shrink the physical footprint and reduce board space requirements.

Intel also trimmed CPU, GPU and NPU resources

Wildcat Lake is not just a cheaper package around an unchanged Panther Lake design.

Intel reduced several major components to better fit the mainstream segment.

The chip supports up to two Xe GPU cores instead of four, while retaining XMX acceleration for AI and removing ray tracing hardware. It also drops from three NPU engines to one, with the NPU rated at 17 TOPS and total platform AI performance at 40 TOPS.

CPU resources are also reduced.

Wildcat Lake supports up to two Performance cores instead of four and cuts LLC from 12MB to 6MB, while Intel says single threaded performance remains comparable.

Other changes include removal of the IPU, reduced media features, a narrower 64 bit LPDDR5 memory interface and fewer display pipelines.

Compute tile area drops by 38%

These changes reduce the compute tile area by 38% compared with the larger Panther Lake configuration.

Intel also cut the I/O tile area by 15% while keeping the features it considers most important for mainstream PCs.

The I/O configuration includes two Thunderbolt or USB4 ports, six PCIe Gen4 lanes, two USB 3.2 ports and eight USB 2.0 ports.

Camera PHYs were removed, and audio resources were reduced to two speakers and microphones with three DSPs and 3MB of memory.

UCIe saves money but increases interface area

The switch from Foveros to UCIe does introduce a tradeoff.

Wildcat Lake uses a 110 micron bump pitch with UCIe, compared with 36 microns on Foveros. That larger pitch requires higher transfer rates and a larger controller area.

Intel says the die to die interface ended up 70% larger than the equivalent Foveros implementation.

Even with that penalty, Intel concluded that the overall MCP design still delivered enough savings to justify the larger interface.

The company also made protocol and power optimizations to reduce the cost and efficiency impact of the UCIe connection.

Platform costs fall beyond the processor package

Intel also reduced costs around the motherboard.

The move to a 64 bit memory interface allows Wildcat Lake systems to use a six layer Type 3 PCB instead of an eight layer design.

Wi Fi 7 is integrated, removing the need for a separate wireless module, while an integrated power delivery controller in the USB retimer cuts additional component requirements.

These changes form part of Intel’s Project Firefly effort to build thinner and more affordable systems around Wildcat Lake.

18A yield recovery helps lower cost

Intel says Wildcat Lake also benefits from better yield recovery on its 18A compute die.

The company can recover around 29% of dies affected by defects in P cores, Xe cores or the NPU by selling them as lower configurations or frequency bins.

Some blocks cannot be disabled because Intel wants consistent battery life and platform behavior. These include the low power E cores, display pipelines and I/O.

That balance allows Intel to salvage more usable silicon while keeping essential features consistent across the Core Series 3 lineup.

Wildcat Lake may share its underlying architecture with Panther Lake, but Intel’s Hot Chips disclosure shows that it has been redesigned extensively around cost. The smaller dies, narrower memory interface, simpler board, reduced feature set and UCIe based organic package all work together to create a lower cost platform without abandoning the core performance and connectivity features Intel wants to retain.