Google is reportedly developing a new TPUv9 accelerator called Triggerfish with MediaTek, aiming to combine AI training and inference capabilities in one chip. The project is expected to target future agentic AI workloads, where models need to switch quickly between reasoning, tool use, training tasks, and real-time responses.
The reported chip would be part of Google’s next Tensor Processing Unit generation and could enter mass production in late 2027 before reaching larger deployment volumes in 2028. Google has not officially confirmed Triggerfish, so the details remain based on supply-chain and analyst reports.
The biggest change is the reported move toward a more flexible TPU design. Instead of separate chips focused mainly on either training or inference, Triggerfish could handle both workloads through a larger memory system and an added CPU tile integrated into the same package.
Triggerfish Could Combine Training and Inference in One TPU
Google’s recent TPU strategy has focused on workload-specific chips. Its TPUv8 lineup included different designs for training and inference, allowing Google to optimise hardware depending on how an AI model was being used.
Triggerfish may take a different direction by combining both roles into one accelerator.
The reported design includes a new CPU tile alongside the main compute die. That CPU component could help manage workload transitions between training and inference tasks, which may become more important as AI agents perform longer and more complex jobs.
| Reported feature | Expected role |
|---|---|
| TPUv9 architecture | Next-generation Google AI accelerator |
| MediaTek involvement | Chip development and backend design support |
| Larger SRAM cache | Keeps more AI workload data closer to the processor |
| Integrated CPU tile | Helps switch between training and inference tasks |
| HBM4E memory | High-bandwidth memory for advanced AI workloads |
| Target market | Agentic AI, training, and inference systems |
The reported SRAM increase could be particularly important. Larger on-chip memory reduces the need to move data back and forth to external memory, which can improve speed and efficiency in AI systems.
HBM4E Memory Could Give the Chip More Bandwidth
Triggerfish is reportedly expected to use HBM4E memory, a newer high-bandwidth memory technology designed for AI accelerators and large data centre systems.
HBM is critical for AI hardware because large language models require huge amounts of memory bandwidth. More bandwidth allows the processor to move model weights, activations, and other data faster during training and inference.
The report suggests Triggerfish may include two to three times more SRAM than the related Humufish TPU design. That combination of larger cache memory and HBM4E could help Google build hardware better suited to agentic AI services.
Agentic AI systems need more than simple prompt-and-response processing. They may have to break down tasks, use tools, access databases, check results, and run multiple model steps before returning an answer. That creates a stronger need for efficient memory management and flexible processing.
MediaTek’s Role in Google’s TPU Program Is Growing
MediaTek has become increasingly important in Google’s custom AI chip plans. The company has already been linked to previous TPU projects, and reports suggest it could take a larger role in future Google accelerators.
Google has worked with several chip partners, including Broadcom, MediaTek, and potentially Intel for advanced packaging. This multi-partner strategy gives Google more flexibility as AI demand grows and supply chains become more difficult to manage.
A reported TPUv9 roadmap includes another chip known as Humufish, which may use HBM4 memory and Intel EMIB packaging. Triggerfish could sit above it as a more advanced design focused on higher performance and broader AI workloads.
Google May Use Intel Packaging Without Moving Chip Production
Reports have suggested that Intel could play a role in packaging some future Google TPU products through its EMIB technology.
EMIB allows multiple chip components to be connected in one package without relying entirely on larger 2.5D packaging methods. It can offer a more flexible and potentially lower-cost approach for complex AI processors.
However, Google may still use TSMC for manufacturing the main chip dies. That would allow the company to combine TSMC’s advanced process technology with Intel’s packaging capabilities.
The final manufacturing strategy remains unclear, and large AI chip projects often change as companies secure foundry capacity, memory supply, and packaging resources.
Triggerfish Shows How AI Chips Are Becoming More Specialised
Google’s reported TPUv9 plans show how quickly custom AI hardware is changing. Companies are no longer building one broad accelerator for every AI task. Instead, they are creating processors tailored for specific workloads, memory needs, power limits, and deployment models.
Triggerfish could help Google run future AI models more efficiently across its cloud services, consumer products, and internal infrastructure. It may also give Google more control over its AI compute supply as demand for Nvidia GPUs and high-bandwidth memory continues to grow.
The project is still far from launch, but the reported design points to a future where AI chips are built around the needs of AI agents rather than only traditional model training or chatbot inference.
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