AMD’s next generation EPYC Venice processors have entered volume production, making them the first high performance computing CPUs to reach that stage on TSMC’s 2nm process. The new server chips are based on AMD’s Zen 6 architecture and are expected to launch later this year.
The milestone matters because demand for data center CPUs is rising as companies build larger AI systems. AMD is positioning Venice as a major platform for AI infrastructure, enterprise servers, and high performance computing. The company also plans to ramp the same EPYC Venice chips at TSMC Arizona, which could help improve supply for customers building AI data centers.
AMD is using Zen 6 and TSMC 2nm to push higher performance and better efficiency
AMD says EPYC Venice will offer more than 70 percent improvement in performance and efficiency, along with more than 30 percent higher thread density. The chips are expected to come in two main versions, including a classic 96 core model and a denser 256 core model with 512 threads. That would be a clear increase over AMD’s current Turin lineup, which tops out at 192 cores and 384 threads.
The move to TSMC’s 2nm process is another key part of the story. The process shifts from FinFET to nanosheet transistors and is said to bring 10 to 15 percent higher performance at the same power, 25 to 30 percent lower power at the same performance, and up to 15 percent higher transistor density.
| Area | EPYC Venice details |
|---|---|
| CPU family | 6th Gen AMD EPYC |
| Architecture | Zen 6 |
| Process node | TSMC 2nm |
| Production status | Volume ramp started |
| Core options | 96 core and up to 256 core variants |
| Maximum threads | Up to 512 threads |
| Claimed improvement | More than 70 percent performance and efficiency gain |
| Target market | AI data centers, enterprise, and HPC |
AMD is also preparing Verano, an AI focused version of Venice designed for agentic AI workloads. Verano is expected to use newer memory standards such as LPDDR to improve bandwidth and efficiency for AI tasks.
The company’s close partnership with TSMC also remains central to its server plans. AMD is using TSMC’s 2nm process for Venice and advanced packaging technologies such as SoIC X and CoWoS L across its broader AI and data center portfolio.
Competition in the AI CPU market is getting stronger. Nvidia is preparing its Vera CPU, Arm based AI chips are also moving forward, and Intel is investing heavily in its own server roadmap. For AMD, the main challenge will be supply. Strong specs matter, but in the AI data center market, the company that can deliver enough chips at scale will have a major advantage.
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