Qualcomm HBC Uses Stacked Compute and LPDDR to Target AI Memory Bottlenecks

Qualcomm has introduced High Bandwidth Compute, or HBC, a new memory architecture designed for AI accelerators that need more capacity and bandwidth without the growing power cost of traditional high bandwidth memory. The technology places a dedicated compute layer beneath stacked LPDDR memory, creating a tightly integrated design intended to reduce one of the biggest limits in modern AI systems.

The company says HBC will appear first in its AI250 accelerator platform, expected in 2027. Qualcomm is also planning a second generation HBC design for its AI300 accelerators in 2028.

HBC is part of Qualcomm’s wider Dragonfly data center strategy, which includes AI accelerators, server CPUs, networking hardware, and custom silicon. The goal is to build infrastructure that can run large language models and agentic AI workloads more efficiently than current systems.

AI Hardware Is Increasingly Limited by Memory

AI processors can perform huge amounts of computation, but they need to move large volumes of data between compute units and memory. As models become larger, memory capacity, bandwidth, and power use can become more important than raw processing speed.

High bandwidth memory is widely used in leading AI accelerators because it delivers fast data access. However, it can increase power use and system cost, especially as AI clusters scale to thousands of processors.

Qualcomm’s HBC approach uses LPDDR memory because it can offer larger capacity at a lower power cost. A dedicated accelerator layer is placed beneath the memory stack and connected through through silicon vias, allowing the components to communicate more directly.

HBC Gen 1 Will Arrive With the AI250 Accelerator

Qualcomm says HBC Gen 1 will be used with its AI250 accelerator platform. The design will place the HBC enhanced LPDDR stack on the same organic substrate as the accelerator.

The company claims each AI250 card can provide up to 133TB per second of bandwidth, which it describes as an 18 times increase over its AI200 platform with LPDDR5X memory. Qualcomm also claims HBC can provide up to six times better bandwidth per watt than HBM and up to 200 times more capacity per watt than SRAM.

Those numbers are Qualcomm’s own projections. They should be treated carefully until finished hardware is available and tested against competing AI accelerators under the same workloads.

Qualcomm Plans a Bigger HBC Upgrade for 2028

The second generation HBC design is expected to arrive with Qualcomm’s AI300 accelerator in 2028. Qualcomm says HBC Gen 2 could deliver up to 54 times more effective bandwidth than the AI200 platform and up to seven times better bandwidth per watt than HBM.

The company is trying to address a growing challenge for AI data centers. Better GPUs and accelerators alone are not enough if memory cannot store and move model data efficiently. Improving bandwidth while lowering energy use could help reduce the cost of running large inference clusters.

HBC Has Ambitious Goals but Still Needs Real World Proof

Qualcomm’s HBC strategy is interesting because it moves away from relying entirely on HBM. LPDDR based memory may offer a different balance of capacity, cost, and power use, especially for inference systems where large memory pools are important.

Still, the technology is early. Qualcomm has not provided independent benchmarks, detailed latency figures, or direct performance results against current HBM based hardware. The first HBC products are also not expected until 2027.

For now, HBC is a major roadmap announcement rather than a shipping product. But it shows how AI hardware companies are searching for new ways to overcome memory limits as models and data center workloads continue to grow.