AMD prepares Zen 6 EPYC Venice reveal for July 22 and 23 at Advancing AI event

AMD is preparing to introduce its next generation EPYC Venice server processors at its Advancing AI event on July 22 and 23. The confirmation came from AMD CTO and executive vice president Mark Papermaster, who said the new server CPU family will be part of the company’s discussion at the event.

Venice is important because it will be AMD’s first EPYC platform based on the Zen 6 architecture. The chips are aimed at enterprise and data center customers that still depend heavily on x86 systems for long running business, cloud, and infrastructure workloads. Papermaster said enterprise customers have decades of x86 software and deployments, and AMD is designing Venice to continue serving those traditional workloads while pushing performance forward.

The launch also comes at a time when AI is reshaping server hardware demand. GPUs and accelerators receive most of the attention, but CPUs remain central to data center design. They handle virtualization, databases, general compute, control tasks, and many workloads that do not move fully to accelerators.

EPYC Venice is expected to bring more cores, faster memory, and PCIe 6 support

The upcoming EPYC Venice lineup is expected to offer up to 256 Zen 6 cores in its flagship configuration. That would be a large increase over AMD’s current EPYC Turin generation, which tops out at 192 cores. AMD is also expected to move Venice to the new SP7 socket, with 16 channel memory support and up to 1.6 TB per second of memory bandwidth.

The platform is also expected to support PCIe 6.0, which matters for modern AI servers because CPUs need faster links to GPUs, accelerators, networking devices, and storage. Higher data movement is becoming just as important as raw compute as server systems become more complex.

AMD has previously said that EPYC Venice production has been moving forward on TSMC’s 2nm process in Taiwan, with future production also planned for TSMC’s Arizona facility. If that schedule holds, Venice will be one of the first high performance computing processor families tied to the advanced node.

The company is claiming a major performance and efficiency step over Zen 5 based EPYC chips. The reference material points to more than 70 percent higher performance and efficiency compared with the previous generation. Real world gains will depend on workload, platform tuning, memory configuration, and power limits, but the direction is clear. AMD wants Venice to strengthen its position in dense server deployments where core count, efficiency, and platform bandwidth all matter.

Client Zen 6 chips are expected later. Mainstream desktop and laptop processors based on Zen 6 are not likely to appear at the same time as EPYC Venice. AMD may wait until CES 2027 to discuss consumer Zen 6 products more broadly.

For now, Venice is clearly a data center focused launch. AMD is using its Advancing AI event to show how Zen 6 fits into the next stage of enterprise compute, where traditional x86 workloads and AI infrastructure are increasingly connected. If the reported specifications hold, EPYC Venice could become one of AMD’s most important server launches in years.