Intel Accelerates Ohio Fab Work as EMIB-T Packaging Yield Nears 90%

Intel is reportedly offering overtime bonuses to speed construction work at its large semiconductor manufacturing complex in Ohio, as the company works toward high volume production using its future 14A process by 2031.

The Ohio site covers roughly 1,000 acres and is intended to support Intel’s advanced Angstrom era manufacturing technologies, including the 18A and 14A process nodes. The additional worker incentives suggest Intel is trying to protect the project’s schedule after delays and rising construction costs affected semiconductor expansion plans across the industry.

Intel is also making progress with EMIB-T, an advanced packaging technology designed to connect processors, memory, and other chiplets inside one package. Package yields are reportedly approaching 90 percent ahead of planned commercial availability in 2027.

However, substrate production remains a major obstacle. Current substrate yields are said to be around 50 percent, which could restrict the number of usable packages Intel can produce at scale.

Intel Wants Ohio Fab Ready for 14A Production by 2031

The Ohio manufacturing complex is a central part of Intel’s effort to expand leading edge semiconductor production in the United States.

Intel plans to use the site for advanced nodes including 18A and 14A. The latter is expected to support future processors and foundry customers later in the decade.

Ohio fab detail	Reported information
Site size	Around 1,000 acres
Planned technologies	Intel 18A and 14A
High volume 14A target	2031
Current action	Overtime bonuses for faster construction
Main purpose	Advanced semiconductor manufacturing
Location	Ohio, United States

Overtime payments can help contractors extend shifts and complete important stages more quickly. They may also increase costs, especially when construction requires specialised workers, equipment, and safety procedures.

Intel has not publicly detailed the value of the bonuses or how much time it expects to save. The incentives indicate that completing the site on schedule remains a priority.

The 2031 target leaves several years for construction, tool installation, process qualification, and customer certification. A semiconductor fab cannot begin high volume manufacturing immediately after its buildings are completed. Production equipment must be installed and calibrated, while each process needs extensive testing before commercial output can begin.

EMIB-T Package Yield Approaches 90%

Intel reportedly plans to offer EMIB-T packaging in volume during 2027.

The technology builds on Intel’s existing Embedded Multi-die Interconnect Bridge system. Standard EMIB uses small silicon bridges embedded inside an organic substrate to connect neighbouring chiplets.

These bridges provide dense connections only where they are needed. This avoids placing every component on one large silicon interposer, which can increase cost and manufacturing complexity.

EMIB-T adds Through-Silicon Vias to the bridges. These vertical electrical paths allow power and signals to travel through the bridge from the lower part of the package to processors or memory positioned above it.

Packaging feature	Standard EMIB	EMIB-T
Embedded silicon bridges	Yes	Yes
High density chiplet links	Yes	Yes
Through-Silicon Vias	No	Yes
Vertical power and signal routing	Limited	Supported
3D stacking potential	Lower	Higher
Planned volume availability	Already used	Reportedly 2027

This design could support more complex combinations of compute chiplets, cache, accelerators, and high bandwidth memory.

Intel’s package yield is said to be nearing 90 percent. That means most completed packages are passing required manufacturing and performance checks.

A high package yield is encouraging, but it does not solve every production challenge because each package still depends on a usable substrate.

Substrate Yield Remains at Around 50%

The substrate is the foundation that holds the bridges, chiplets, and electrical connections together.

Intel’s EMIB-T substrate reportedly contains an organic base panel with precision cut cavities for the silicon bridges. Insulating build-up layers are placed over the embedded structures, while the bridges contain the vertical vias needed for power and signal routing.

EMIB-T substrate component	Function
Organic base panel	Supports the entire package
Precision cavities	Hold the silicon bridges
Build-up insulation layers	Separate and protect electrical paths
Silicon bridges	Connect neighbouring chiplets
Through-Silicon Vias	Carry signals and power vertically
Micro-bumps	Create dense chip-to-bridge connections

The organic panels are produced by several substrate suppliers, while the build-up layers use a common insulating material known as Ajinomoto Build-up Film.

Producing these substrates requires tight alignment and precise manufacturing. Defects in the cavities, bridge placement, layers, or electrical connections can make the entire substrate unusable.

A reported yield of 50 percent means only about half of the substrates currently meet requirements. Even if final package assembly reaches a 90 percent yield, the earlier substrate losses can still limit total output and raise the cost of every completed product.

Improving this figure will therefore be essential before Intel can offer EMIB-T in large volumes.

EMIB-T Could Compete With Larger Interposer Designs

Advanced packaging has become increasingly important as processor companies move away from building every function on one large chip.

Chiplet designs allow manufacturers to combine dies produced using different processes. A processor can use advanced nodes for compute cores while relying on older, cheaper technologies for input and output functions.

The challenge is connecting those components with enough bandwidth and low enough latency.

Large silicon interposers offer dense connectivity, but they can be expensive and difficult to manufacture. Intel’s embedded bridge approach places smaller pieces of silicon only between the chiplets that need high speed links.

EMIB-T is reportedly around 50 percent less expensive than some competing large interposer packaging methods. The final cost will depend on package size, memory configuration, manufacturing volume, and substrate yield.

A lower cost solution could help Intel attract foundry customers building AI accelerators, data centre processors, and other large chiplet products.

Intel Still Needs to Improve Manufacturing Consistency

The reported progress gives Intel two positive signals.

Its Ohio construction programme appears to remain active, while EMIB-T package assembly is achieving a strong yield before its planned volume launch.

The remaining problems are still significant. The Ohio fab must stay on schedule through several more years of construction and equipment installation, and EMIB-T substrate yield must rise well above its current level.

Intel project	Positive development	Remaining challenge
Ohio fab	Overtime incentives may accelerate work	Construction and production qualification
Intel 14A	High volume target remains 2031	Process maturity and customer demand
EMIB-T packaging	Package yield approaching 90%	Volume production not expected until 2027
EMIB-T substrate	Multiple suppliers involved	Yield reportedly near 50%
Foundry competition	Potentially lower packaging cost	Must prove reliability at scale

Substrate yield improvements are common during the early stages of a new packaging platform. Suppliers refine materials, equipment settings, inspection methods, and manufacturing tolerances as production expands.

Intel’s ability to solve that problem will determine whether EMIB-T becomes a broadly available commercial service or remains limited to selected products.

The Ohio fab and EMIB-T represent different parts of the same strategy. Intel is trying to rebuild its manufacturing position while offering customers more advanced ways to assemble large processors. Progress is visible, but both efforts still depend on years of execution before they can deliver their intended scale.