AMD has introduced the Instinct MI455X, a new data centre accelerator designed for frontier AI training, large scale inference and future AI factory deployments.
The MI455X will power AMD’s Helios rack scale platform and forms part of the wider Instinct MI400 family. It uses the CDNA 5 architecture, combines TSMC 2nm and 3nm process technologies and contains around 320 billion transistors.
AMD is positioning the accelerator directly against NVIDIA’s Rubin GPU. The MI455X offers 432GB of HBM4 memory, which is 50% more capacity than Rubin’s reported 288GB. AMD also claims up to 40 PFLOPs of FP4 compute and 20 PFLOPs of FP8 performance.
The company says the MI455X is intended for large AI models that need substantial memory capacity, fast communication between accelerators and flexible partitioning across different workloads.
| Specification | AMD Instinct MI455X |
|---|---|
| Architecture | CDNA 5 |
| Transistor count | 320 billion |
| Compute process | TSMC 2nm |
| Input output and cache process | TSMC 3nm |
| Accelerator dies | Eight XCDs |
| HBM capacity | 432GB HBM4 |
| Memory bandwidth | Up to 23.3TB/s |
| FP4 compute | 40 PFLOPs |
| FP8 compute | 20 PFLOPs |
| Shared cache | 192MB |
| Main rack platform | AMD Helios |
The MI455X uses a large chiplet design with advanced packaging
AMD has built the MI455X around a modular chiplet architecture rather than a single large die.
The accelerator includes eight XCD compute dies connected through AMD Infinity Fabric. These dies are combined with separate input output, fabric and cache components.
AMD uses CoWoS-L packaging and 3D hybrid bonding to connect the different parts of the GPU. The company says this approach improves die-to-die bandwidth, lowers communication latency and increases compute density.
Each XCD contains 32 workgroup processors, giving the chip 256 active WGPs across the eight compute dies. The design reportedly includes additional disabled resources to improve manufacturing yields.
The chip also contains twelve 16MB cache blocks, creating 192MB of shared last-level cache.
This internal structure is designed to support operations that distribute data and model components across the full accelerator. Examples include tensor parallelism, expert parallelism and key value cache sharing.
HBM4 capacity is the MI455X’s main advantage over Rubin
Memory is one of the most important differences between the MI455X and NVIDIA Rubin.
AMD’s accelerator includes 432GB of HBM4 connected through twelve memory controllers. This represents a 50% capacity increase over the 288GB of HBM3E used by the earlier MI350 series.
It also gives the MI455X 50% more memory than the reported 288GB HBM4 configuration on Rubin.
Larger memory capacity allows a single accelerator to hold more model weights, larger context windows and more inference data without moving information between separate GPUs or slower system memory.
That can simplify deployment for very large models and reduce communication overhead.
Memory bandwidth reaches up to 23.3TB/s, compared with around 8TB/s on the MI350 series. This is close to Rubin’s reported bandwidth of approximately 22TB/s.
AMD therefore appears to be prioritising greater capacity while remaining competitive in bandwidth.
AMD and NVIDIA lead in different compute formats
The MI455X is rated for 40 PFLOPs of FP4 compute and 20 PFLOPs of FP8 performance.
NVIDIA Rubin is reported to offer 50 PFLOPs at FP4 and 17.5 PFLOPs at FP8.
This gives NVIDIA the advantage in the stated FP4 figure, while AMD leads in FP8.
| Accelerator | FP4 compute | FP8 compute | HBM4 capacity | Memory bandwidth |
|---|---|---|---|---|
| AMD Instinct MI455X | 40 PFLOPs | 20 PFLOPs | 432GB | Up to 23.3TB/s |
| NVIDIA Rubin | 50 PFLOPs | 17.5 PFLOPs | 288GB | Around 22TB/s |
These headline specifications do not determine final application performance on their own.
Real results will depend on software optimisation, power use, networking, model type, numerical precision and how well workloads scale across several accelerators.
NVIDIA continues to benefit from its mature CUDA ecosystem. AMD is relying on ROCm and open software standards to attract customers that want more flexibility and less dependence on one vendor.
Helios will combine MI455X GPUs with Zen 6 EPYC processors
The MI455X is designed to operate inside AMD’s Helios rack scale AI platform.
Helios combines Instinct accelerators, Zen 6 EPYC processors, networking, memory and software in a complete system.
AMD says the platform is intended for frontier model training, high volume inference and large AI factory deployments.
The company claims the MI455X provides the same general level of FP4 and FP8 compute, memory bandwidth and scale-up networking as competing systems, while offering 1.5 times more memory capacity and up to 1.5 times more scale-out bandwidth.
Those claims will need to be evaluated in complete rack configurations because communication between GPUs can matter as much as the performance of an individual accelerator.
AMD is also emphasising security through encrypted GPU links, secure boot and hardware protections for sensitive workloads.
Partitioning allows one accelerator to serve several workloads
The MI455X supports NUMA configurations and up to eight spatial partitions.
Its NPS1 mode distributes memory access across all twelve HBM stacks, while NPS2 divides access across smaller groups without crossing between dies.
The eight XCDs can also operate as separate partitions.
This allows data centre operators to divide one accelerator among multiple jobs or customers instead of dedicating the entire device to one workload.
Partitioning can improve utilisation in cloud environments where different tasks require different levels of compute and memory.
It can also help separate workloads for security or operational reasons.
The MI430X will focus more heavily on HPC
The MI400 family includes more than one accelerator.
The MI455X and MI450X are aimed primarily at AI training and inference. The MI430X is designed for high-performance computing and sovereign AI.
AMD says the MI430X can deliver up to 288 TFLOPs of hardware FP64 performance, making it better suited to scientific simulation and other workloads that require higher numerical precision.
It also uses 432GB of HBM4 and offers similar memory bandwidth to the MI455X.
This product split allows AMD to target both AI workloads that favour lower precision formats and traditional HPC applications that depend on FP64 accuracy.
AMD plans annual Instinct upgrades after MI400
AMD is moving its data centre accelerator roadmap towards a yearly release cycle.
The MI500 family, based on CDNA 6, is expected in 2027. MI600, using a later CDNA architecture, is planned for 2028.
This follows a strategy similar to NVIDIA’s regular accelerator updates and allows AMD to respond more quickly to changes in model size, memory requirements and networking demands.
The MI455X is therefore an important step, but it is also part of a much faster development schedule.
Its main strengths are clear from the announced specifications. AMD is offering exceptionally large HBM4 capacity, strong FP8 performance, advanced chiplet packaging and integration into a complete Helios rack.
Whether it can take meaningful market share from NVIDIA will depend on ROCm adoption, availability, pricing and how well Helios performs in real AI deployments.
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